PART |
Description |
Maker |
M5LV-512/256-10SAI M5LV-512/256-12SAC M5LV-256/160 |
EE PLD, 10 ns, PBGA352 BGA-352 EE PLD, 12 ns, PBGA352 BGA-352 Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP208 Fifth Generation MACH Architecture EE PLD, 12 ns, PQFP208 Fifth Generation MACH Architecture EE PLD, 20 ns, PQFP160 Fifth Generation MACH Architecture EE PLD, 5.5 ns, PQFP100 Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP160 Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP160 EE PLD, 15 ns, PBGA352 BGA-352 Fifth Generation MACH Architecture EE PLD, 5.5 ns, PQFP144 EE PLD, 15 ns, PQFP160 PLASTIC, QFP-160 CONNECTOR ACCESSORY EE PLD, 5.5 ns, PQFP100 Fifth Generation MACH Architecture EE PLD, 15 ns, PQFP208 Fifth Generation MACH Architecture EE PLD, 7.5 ns, PQFP208 Fifth Generation MACH Architecture EE PLD, 10 ns, PQFP100 EE PLD, 15 ns, PQFP100 TQFP-100 Fifth Generation MACH Architecture EE PLD, 20 ns, PQFP208 EE PLD, 12 ns, PQFP100 TQFP-100 EE PLD, 12 ns, PBGA256 BGA-256
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Lattice Semiconductor, Corp. LATTICE SEMICONDUCTOR CORP
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CY7C1474V33-167BGC CY7C1470V33-250AXC CY7C1470V33- |
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture ECONOLINE: RQS & RQD - 1kVDC Isolation- Internal SMD Construction- UL94V-0 Package Material- Toroidal Magnetics- Efficiency to 80% 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 4M X 18 ZBT SRAM, 3 ns, PBGA165 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 4M X 18 ZBT SRAM, 3.4 ns, PBGA165 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 1M X 72 ZBT SRAM, 3.4 ns, PBGA209 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 2M X 36 ZBT SRAM, 3.4 ns, PBGA165
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Cypress Semiconductor Corp. Cypress Semiconductor, Corp.
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CY7C1350F CY7C1350F-100AC CY7C1350F-100AI CY7C1350 |
4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PBGA119 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 4.5 ns, PQFP100 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PBGA119 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.6 ns, PQFP100 CABLE ASSEMBLY; LEAD-FREE SOLDER; SMA MALE TO SMA MALE; 50 OHM, PE-SR047FL (.047" RE-SHAPABLE) 128K X 36 ZBT SRAM, 3.5 ns, PQFP100 4-Mb (128K x 36) Pipelined SRAM with Nobl Architecture 128K X 36 ZBT SRAM, 2.8 ns, PQFP100 4-Mb (128K x 36) Pipelined SRAM with Nobl(TM) Architecture
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Cypress Semiconductor, Corp. Cypress Semiconductor Corp. CYPRESS[Cypress Semiconductor]
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CAT64LC20ZS CAT64LC20ZP CAT64LC20J-TE7 CAT64LC20J- |
36-Mbit QDR-II SRAM 4-Word Burst Architecture 36-Mbit QDR-II SRAM 2-Word Burst Architecture 9-Mbit (256K x 36/512K x 18) Pipelined SRAM with NoBL Architecture 4-Mbit (128K x 36) Pipelined SRAM with NoBL Architecture 4-Mbit (128K x 36) Flow-through SRAM with NoBL Architecture 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture SPI Serial EEPROM SPI串行EEPROM 36-Mbit QDR™-II SRAM 2-Word Burst Architecture SPI串行EEPROM 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM SPI串行EEPROM 256K (32K x 8) Static RAM SPI串行EEPROM
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Analog Devices, Inc. Electronic Theatre Controls, Inc.
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CAT64LC40ZJ CAT64LC40ZS CAT64LC40J-TE7 CAT64LC40J- |
72-Mbit QDR-II SRAM 2-Word Burst Architecture 72-Mbit QDR-II SRAM 4-Word Burst Architecture 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM with NoBL Architecture 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL Architecture SPI Serial EEPROM SPI串行EEPROM 72-Mbit QDR-II™ SRAM 2-Word Burst Architecture SPI串行EEPROM 72-Mbit QDR™-II SRAM 2-Word Burst Architecture
|
Analog Devices, Inc.
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M38230G4-XXXFP M38230G4-XXXHP M38231G4-XXXHP M3823 |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 3.1 to 3.6 V 18-Mbit (512K x 36/1M x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2 M x 18/512K x 72) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 3.1 to 3.6 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 36 Mb; Organization: 512Kb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 1Mb x 72; Vcc (V): 3.1 to 3.6 V 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency); Architecture: QDR-II , 4 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 72-Mbit DDR-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency); Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit(2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 2.4 to 2.6 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit QDR(TM)-II SRAM 4-Word Burst Architecture; Architecture: QDR-II, 4 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 单芯8位CMOS微机 Sync SRAM; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 36-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 36 Mb; Organization: 1Mb x 36; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V 36-Mbit QDR(TM)-II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 36 Mb; Organization: 2Mb x 18; Vcc (V): 1.7 to 1.9 V
|
Renesas Electronics Corporation. Renesas Electronics, Corp.
|
CY7C1371D-100AXI CY7C1371D-100BGI CY7C1373D-100BZI |
18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 8.5 ns, PQFP100 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 18兆位(为512k × 36/1M × 18)流体系结构,通过与NoBLTM的SRAM 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 8.5 ns, PBGA165 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA119 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA165 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PQFP100 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 1M X 18 ZBT SRAM, 6.5 ns, PBGA165 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBLTM Architecture 512K X 36 ZBT SRAM, 8.5 ns, PBGA119
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Cypress Semiconductor Corp. Cypress Semiconductor, Corp.
|
CY7C1333 7C1333 CY7C1333-66AC CY7C1333-50AC |
64Kx32 Flow-Thru SRAM with NoBL Architecture(B>NoBL结构4Kx32流通式 SRAM) 64Kx32 Flow-Thru SRAM with NoBL⑩ Architecture From old datasheet system
|
Cypress Semiconductor Corp.
|
DAT48060 |
Attenuator 4 Section
|
DAICO[DAICO Industries, Inc.]
|
DA0620 |
Attenuator 5 Section
|
DAICO[DAICO Industries, Inc.]
|
CY7C1350 7C1350 |
128Kx36 Pipelined SRAM with NoBL Architecture(带NoBL结构28Kx36流水线式 SRAM) 128K × 36至流水线与总线延迟静态存储器体系结构(带总线延迟结构28K × 36至流水线式的SRAM 128Kx36 Pipelined SRAM with NoBL Architecture(B>NoBL结构28Kx36流水线式 SRAM) From old datasheet system
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Cypress Semiconductor Corp.
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